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| 1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. precision low noise jfet operational amplifiers isl28110, isl28210 the isl28110, isl28210, are single and dual jfet amplifiers featuring low noise, high slew rate, low input bias current and offset voltage, making them the ideal choice for high impedance applications where precision and low noise are important. the combination of pr ecision, low noise, and high speed combined with a small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for these amplifiers include precision medical and analytical instru mentation, sensor conditioning, precision power supply controls, industrial controls and photodiode amplifiers. the isl28110 single amplifier is available in the 8 ld soic, tdfn, and msop packages. the isl28210 dual amplifier is available in the 8 ld soic and tdfn packages. all devices are offered in standard pin configurations and operate over the extended temperature range from -40 c to +125 c. features ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 40v ? low voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6nv/ hz ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2pa ? high slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23v/s ? high bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5mhz ? low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 300v, ma x ? offset drift . . . . . . . . . . . . . . . . . . . . . . . . . . grade c 10v/ c ? low current consumption . . . . . . . . . . . . . . . . . . . . . . 2.55ma ? operating temperature range. . . . . . . . . . .-40 c to +125 c ? small package offerings in single, and dual ? pb-free (rohs compliant) applications ? precision instruments ? photodiode amplifiers ? high impedance buffers ? medical instrumentation ? active filter blocks ? industrial controls related literature ? an1594 isl28210soiceval1z evaluation board user?s guide figure 1. typical application figure 2. in put bias current vs common mode input voltage - + output v + r sh v - basic application circuit - photodiode amplifier photo c t r f diode c f v cm (v) -10 -8 -6 -4 -2 0 2 4 6 8 10 -15 -10 -5 0 5 10 15 v s = 15v normalized input bias current (pa) september 14, 2011 fn6639.2
isl28110, isl28210 2 fn6639.2 september 14, 2011 pin configurations isl28110 (8 ld tdfn) top view isl28110 (8 ld, soic, msop) top view isl28210 (8 ld tdfn) top view isl28210 (8 ld soic) top view 2 3 4 1 7 6 5 8 nc -in a +in a v - nc v + v out a nc + - pad nc -in a +in a v - 1 2 3 4 8 7 6 5 nc v + v out a nc + - 2 3 4 1 7 6 5 8 v out a -in a +in a v - v + v out b -in b +in b + - +- pad v out a -in a +in a v - 1 2 3 4 8 7 6 5 v + v out b -in b +in b + - + - pin descriptions isl28110 (8 ld tdfn) isl28110 (8 ld soic, 8 ld msop) isl28210 (8 ld tdfn) isl28210 (8 ld soic) pin name equivalent circuit description 3 3 3 3 +in a circuit 1 amplifier a non-inverting input 2 2 2 2 -in a circuit 1 amplifier a inverting input 6611v out a circuit 2 amplifier a output 4444v - circuit 3 negative power supply 5 5 +in b circuit 1 amplifier b non-inverting input 6 6 -in b circuit 1 amplifier b inverting input 77v out b circuit 2 amplifier b output 7788v + circuit 3 positive power supply 1, 5, 8 1, 5, 8 no connect pad pad pad thermal pad is electrically isolated from active circuitry. pad can float, connect to ground or to a potential source that is free from signals or noise sources. circuit 2 circuit 1 v + v - circuit 3 in- v + v - in+ capacitively triggered esd clamp v + v - out isl28110, isl28210 3 fn6639.2 september 14, 2011 ordering information part number (notes 1, 2, 3) part marking tcv os (v/c) package (pb-free) pkg. dwg. # isl28110fbz 28110 fbz -c 10 (c grade) 8 ld soic m8.15e isl28210fbz 28210 fbz -c 10 (c grade) 8 ld soic m8.15e coming soon isl28110frtz -c 8110 10 (c grade) 8 ld tdfn l8.3x3a coming soon isl28210frtz -c 8210 10 (c grade) 8 ld tdfn l8.3x3a coming soon isl28110frtbz 8110 4 (b grade) 8 ld tdfn l8.3x3a coming soon isl28210frtbz 8210 4 (b grade) 8 ld tdfn l8.3x3a coming soon isl28110fbbz 28110 fbz -c 4 (b grade) 8 ld soic m8.15e coming soon isl28210fbbz 28210 fbz 4 (b grade) 8 ld soic m8.15e coming soon isl28110fubz 8110z 4 (b grade) 8 ld msop m8.118 coming soon isl28110fuz 8110z 10 (c grade) 8 ld msop m8.118 isl28210soiceval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications.. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28110, isl28210 . for more information on msl please see techbrief tb363 . isl28110, isl28210 4 fn6639.2 september 14, 2011 absolute voltage ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42v maximum supply turn on voltage slew rate. . . . . . . . . . . . . . . . . . . 1v/s maximum differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v - - 0.5v to v + + 0.5v max/min input current for input voltage >v+ or isl28110, isl28210 6 fn6639.2 september 14, 2011 electrical specifications v s = 15v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. parameter description conditions min (note 8) typ max (note 8) units input characteristics v os input offset voltage -300 300 v -40c < t a < +125c -1300 1300 v tcv os input offset voltage temperature coefficient (grade c) -40c < t a < +125c 110 v/c i b input bias current isl28110 4.5 2 4.5 pa -40c < t a < +60c -25 25 pa -40c < t a < +85c -85 85 pa -40c < t a < +125c -950 950 pa i b input bias current isl28210 5 2 5 pa -40c < t a < +60c -350 350 pa -40c < t a < +85c -700 700 pa -40c < t a < +125c -3600 3600 pa i os input offset current isl28110 -2.5 0.5 2.5 pa -40c < t a < +60c -25 25 pa -40c < t a < +85c -85 85 pa -40c < t a < +125c -650 650 pa i os input offset current isl28210 -2.5 0.5 2.5 pa -40c < t a < +60c -285 285 pa -40c < t a < +85c -445 445 pa -40c < t a < +125c -2000 2000 pa c in-diff differential input capacitance 8.3 pf c in-cm common mode input capacitance 11.8 pf r in-diff differential input resistance 530 g r in-cm common mode input resistance 560 g v cmir common mode input voltage range guaranteed by cmrr test v - +1.5 v + -1.5 v cmrr common mode rejection ratio v cm = -13.5v to +13.5v 80 100 db a vol open-loop gain r l = 10k to ground v o = -12.5v to +12.5v 107 109 db -40c < t a < +125c 106 db dynamic performance gbwp gain-bandwidth product g = 100, r l = 100k , c l = 4pf 11 12.5 mhz sr slew rate, v out 20% to 80% g = -1, r l = 2k , 10v step 20 v/s thd+n total harmonic distorti on + noise g = 1, f = 1khz, 10v p-p , r l = 2k 0.00025 % g = 1, f = 1khz, 10v p-p , r l = 600 0.0003 % t s settling time to 0.1% 10v step; 10% to v out a v = 1, v out = 10v p-p , r l =2k to v cm 1.3 s settling time to 0.01% 10v step; 10% to v out a v = 1, v out = 10v p-p , r l =2k to v cm 1.6 s isl28110, isl28210 7 fn6639.2 september 14, 2011 noise performance e np-p peak-to-peak input voltage noise 0.1hz to 10hz 600 nv p-p e n input voltage noise spectral density f = 10hz 18 nv/ hz f = 100hz 7.8 nv/ hz f = 1khz 6 nv/ hz f = 10khz 6 nv/ hz i n input current noise spectral density f = 1khz 9 fa/ hz output characteristics v ol output voltage low, v out to v - r l = 10k 0.8 1.0 v 1.1 v r l = 2k 0.9 1.1 v 1.2 v v oh output voltage high, v + to v out r l to gnd = 10k 0.8 1.0 v 1.1 v r l to gnd = 2k 0.9 1.1 v 1.2 v i sc output short circuit current r l = 10 to v+. v- 50 ma power supply psrr power supply rejection ratio v s = 4.5v to 20v 102 115 db 100 db i s supply current/amplifier 2.55 3.1 ma 3.9 ma note: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v s = 15v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter description conditions min (note 8) typ max (note 8) units isl28110, isl28210 8 fn6639.2 september 14, 2011 typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. figure 3. input offset voltage (v os ) distribution figure 4. t c v os distribution, -40c to +125c figure 5. input bias current (i b ) vs supply voltage figure 6. isl28110 input bias current (i b ) vs temperature figure 7. isl28210 input bias current (i b ) vs temperature figure 8. isl28110 input offset current (i os ) vs temperature v os (v) number of amplifiers 0 50 100 150 200 250 -150 -100 -50 0 50 100 150 200 250 v s = 15v number of amplifiers tcv os (v/c) 0 5 10 15 20 25 - 1 0 - 8 - 6 - 4 - 2 0 2 4 6 8 1 0 v s = 15v t a = -40c to +125c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 56789101112131415 v supply (v) i n p u t b i a s c u r r e n t ( p a ) -80 -70 -60 -50 -40 -30 -20 -10 10 -40 -20 0 20 40 60 80 100 120 140 temperature (c) 0 v s = 15v v s = 5v i b (pa) -40 -20 0 20 40 60 80 100 120 140 i n p u t b i a s ( p a ) temperature (c) -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 v s = 15v v s = 5v -40 -20 0 20 40 60 80 100 120 140 temperature (c) -20 -10 0 10 20 i o s ( p a ) v s = 15v v s = 5v isl28110, isl28210 9 fn6639.2 september 14, 2011 figure 9. isl28210 input offset current (i os ) vs temperature, v s = 5v figure 10. isl28210 input offset current (i os ) vs temperature, v s = 15v figure 11. normalized input bias current (i b ) vs input common mode voltage (v cm ), v s = 5v figure 12. normalized input bias current (i b ) vs input common mode voltage (v cm ), v s = 15v figure 13. normalized input offset voltage (v os ) vs input common mode voltage (v cm ), v s = 5v figure 14. normalized input offset voltage (v os ) vs input common mode voltage (v cm ), v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. (continued) -40 -20 0 20 40 60 80 100 120 140 temperature (c) -20 -10 0 10 20 i o s ( p a ) v s = 5v i os cha i os chb -40 -20 0 20 40 60 80 100 120 140 temperature (c) i o s ( p a ) -50 0 50 100 150 200 250 300 v s = 15v i os cha i os chb -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -5 -4 -3 -2 -1 0 1 2 3 4 5 v cm (v) v s = 5v normalized input bias current (pa) v cm (v) -10 -8 -6 -4 -2 0 2 4 6 8 10 -15 -10 -5 0 5 10 15 v s = 15v normalized input bias current (pa) -500 -400 -300 -200 -100 0 100 200 300 400 500 -5 -4 -3 -2 -1 0 1 2 3 4 5 n o r m a l i z e d v o s ( u v ) v cm (v) v s = 5v -500 -400 -300 -200 -100 0 100 200 300 400 500 n o r m a l i z e d v o s ( u v ) v cm (v) -15 -10 -5 0 5 10 15 v s = 15v isl28110, isl28210 10 fn6639.2 september 14, 2011 figure 15. input noise voltage (e n ) and current (i n ) vs frequency , v s = 5v figure 16. input noise voltage (e n ) and current (i n ) vs frequency , v s = 18v figure 17. 0.1hz to 10hz v p-p noise voltage, v s =5v figure 18. 0.1hz to 10hz v p-p noise voltage, v s = 18v figure 19. thd+n vs frequency vs temperature, a v = 1, 10, v out = 10v p-p , r l = 600 figure 20. thd+n vs frequency vs temperature, v out = 10v p-p , r l = 2k typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. (continued) 1 10 100 1000 1 10 100 1000 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o lta g e ( nv / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( f a / h z ) v s = 5v input noise voltage input noise current 1 10 100 1000 1 10 100 1000 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o lta g e ( nv / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( f a / h z ) v s = 18v input noise voltage input noise current i n p u t n o i s e v o lta g e ( nv p - p ) 012345678910 time (s) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 v s = 5v a v = 10k i n p u t n o i s e v o lta g e ( nv p - p ) 012345678910 time (s) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 v s = 18v a v = 10k 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k t h d + n ( % ) frequency (hz) a v = 1 a v = 10 v s = 15v c l = 4pf v out = 10v p-p r l = 600 c-weighted 22hz to 500khz +125c -40c +25c -40c +25c +125c a v = 1 a v = 10 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k t h d + n ( % ) frequency (hz) v s = 15v c l = 4pf v out = 10v p-p r l = 2k c-weighted 22hz to 500khz +125c -40c +25c -40c +25c +125c isl28110, isl28210 11 fn6639.2 september 14, 2011 figure 21. thd+n vs output voltage (v out ) vs temperature, a v = 1 f = 1khz, r l = 600 figure 22. thd+n vs output voltage (v out ) vs temperature, a v = 1 f =1khz, r l = 2k figure 23. crosstalk vs frequency figure 24. small signal overshoot vs load capacitance (c l ) figure 25. open loop gain-phase vs frequenc y figure 26. closed loop gain vs frequency typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. (continued) 0.0001 0.001 0.01 0.1 1 0 5 10 15 20 25 30 v out (v p-p ) t h d + n ( % ) a v = 1 v s = 15v c l = 4pf f = 1khz r l = 600 c-weighted 22hz to 22khz -40c +25c +125c 0.0001 0.001 0.01 0.1 1 0 5 10 15 20 25 30 v out (v p-p ) t h d + n ( % ) a v = 1 v s = 15v c l = 4pf f = 1khz r l = 2k c-weighted 22hz to 22khz -40c +25c +125c -140 -120 -100 -80 -60 -40 -20 0 1 10 100 1k 10k 100k 1m 10m 100m c r o s s t a l k ( d b ) frequency (hz) v s = 15v c l = 4pf v cm = 1v p-p r l - transmit = 2k r l _ receive = 10k r l - transmit = r l _ receive = o v e r s h o o t ( % ) load capacitance (nf) 0 10 20 30 40 50 60 0.001 0.01 0.1 1 10 100 v s = 15v v out = 100mv p-p a v = 10 a v = -1 a v = 1 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 100 1k 10k 100k 1m 10m 100m 1g g a i n ( d b ) frequency (hz) v s = 15v r l =1m ? gain phase -10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m 100m g a i n ( d b ) frequency (hz) a cl = 1 a cl = 10 a cl = 100 a cl = 1000 v s = 5v & 15v c l = 4pf v out = 100mv p-p r l = open r f = 100k ? , r g = 100 ? r f = 100k ? , r g = 1k ? r f = 100k ? , r g = 10k ? r f = 0, r g = isl28110, isl28210 12 fn6639.2 september 14, 2011 figure 27. power supply rejection ratio (psrr) vs frequency figure 28. common-mode rejection ratio (cmrr) vs frequency figure 29. output voltage (v out ) vs output current (i out ) vs temperature, v s = 5v figure 30. output voltage (v out ) vs output current (i out ) vs temperature, v s = 15v figure 31. positive output overload recovery time figure 32. negative output overload recovery time typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. (continued) 10 100 1k 10k 100k 1m 10m p s r r ( db ) frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 v s = 15v c l = 4pf v cm = 1v p-p r l = 10k a v = 1 psrr- psrr+ 0.1 1 10 100 1k 10k 100k 1m 10m 100m c m r r ( db ) frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 v s = 15v simulation v o h 0 10203040506070 v o l i-force (ma) 1 2 3 4 5 -5 -4 -3 -2 -1 v s = 5v a v = 2 v in = 2.5v p-p r f = r g = 100k 0c -40c +25c +85c +125c 10 11 12 13 14 15 v o h -15 -14 -13 -12 -11 -10 0 10203040506070 v o l i-force (ma) v s = 15v a v = 2 v in = 7.5v p-p r f = r g = 100k -40c 125c 85c 25c 0c 0 2 4 6 8 101214161820 o u tp u t ( v ) i n p u t ( m v ) time (s) 0 4 8 12 16 20 0 40 80 120 160 200 v s = 15v a v = 100 v in = 100mv p-p overdrive = 1v r l = 10k a v = 1 input output o u tp u t ( v ) 0 2 4 6 8 10 12 14 16 18 20 i n p u t ( m v ) time (s) -20 -16 -12 -8 -4 0 -200 -160 -120 -80 -40 0 v s = 15v a v = 100 v in = 100mv p-p overdrive = 1v r l = 10k input output isl28110, isl28210 13 fn6639.2 september 14, 2011 figure 33. slew rate vs inverting closed loop gain, v s = 5v figure 34. slew rate vs inverting closed loop gain, v s =15v figure 35. slew rate vs non-inverting closed loop gain, v s = 5v figure 36. slew rate vs non-inverting closed loop gain, v s =15v figure 37. small signal transient response figure 38. large signal unity gain transient response typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. (continued) 0 5 10 15 20 25 30 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 s le w r a te ( v / s ) gain v s = 5v v out-pp = 4v r l = 2k c l = 4pf +sr -sr 0 5 10 15 20 25 30 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 s le w r a te ( v / s ) gain v s = 15v v out-pp = 10v r l = 2k c l = 4pf -sr +sr 0 5 10 15 20 25 30 10 9 8 7 6 5 4 3 2 1 s le w r a te ( v / s ) gain v s = 5v v out-pp = 4v r l = 2k c l = 4pf -sr +sr 0 5 10 15 20 25 30 10 9 8 7 6 5 4 3 2 1 s le w r a te ( v / s ) gain v s = 15v v out-pp = 10v r l = 2k c l = 4pf +sr -sr -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v o u t ( v ) time (s) v s = 15v a v = 1 r l = 2k c l = 4pf -6 -4 -2 0 2 4 6 012345678910 v s = 15v a v = 1 r l = 2k c l = 4pf v o u t ( v ) time (s) isl28110, isl28210 14 fn6639.2 september 14, 2011 applications information functional description the isl28110 and isl28210 are single and dual 12.5 mhz precision jfet input op amps. these devices are fabricated in the pr40 advanced silicon-on-insulator (soi) bipolar-jfet process to ensure latch-free operation. the precision jfet input stage provides low input offset voltage (300v max @ +25 c), low input voltage noise (6nv/ hz), and input current noise that is very low with virtually no 1/f component. a high current complementary npn/pnp emitter-follower output stage provides high slew rate and maintains excellent thd+n performance into heavy loads (0.0003% @ 10v p-p @ 1khz into 600 ). operating voltage range the devices are designed to operate over the 9v (4.5v) to 40v (20v) range and are fully characterized at 10v (5v) and 30v (15v). the jfet input stage maintains high impedance over a maximum input differential voltage range of 33v. internal esd protection diodes clamp the non-inverting and inverting inputs to one diode drop above and below the v+ and v- the power supply rails (?pin descriptions? on page 2, circuit 1). input esd diode protection the jfet gate is a reverse-bi ased diode with >33v reverse breakdown voltage which enables the device to function reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on mosfet and most bipolar input stage op amps. no special input signal restrictions are needed for power supply operation up to 15v, and input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. for power supply operation greater than 16v (>32v), the internal esd clamp diodes alone cannot clamp the maximum input differential signal to the po wer supply rails without the risk of exceeding the 33v breakdown of the jfet gate. under these conditions, differential input voltage limiting is necessary to prevent damage to the jfet input stage. in applications where one or both amplifier input terminals are at risk of exposure to voltages be yond the supply rails, current limiting resistors may be needed at each input terminal (see figure 39. large signal 10v step response a v = -1 figure 40. large signal 10v step response a v = +10 figure 41. settling time (t s ) vs closed loop gain figure 42. z out vs frequency typical performance curves v s = 15v, v cm = 0v, r l = open, t = +25c, unless otherwise specified. (continued) -6 -4 -2 0 2 4 6 012345678910 v o u t ( v ) time (s) v s = 15v a v = -1 r l = 2k c l = 4pf v s = 15v a v = +10 r l = 2k c l = 4pf -6 -4 -2 0 2 4 6 012345678910 v o u t ( v ) time (s) 1 10 100 0.1 1 10 100 closed loop gain (v/v) settling time (s) v s = 15v 0.01% 0.1% v out = 10v p-p r l = 2k ? 0.01 0.1 1 10 100 1000 10 100 1k 10k 100k 1m 10m 100m z ou t ( ? ) frequency (hz) v s = 15v g = 1 g = 10 g = 100 isl28110, isl28210 15 fn6639.2 september 14, 2011 figure 43 r in +, r in -) to limit current through the power supply esd diodes to 20ma. jfet input stage performance the isl28110, isl28210 jfet input stage has the linear gain characteristics of the mosfet bu t can operate at high frequency with much lower noise. the reversed-biased gate pn gate junction has significantly lower gate capacitance than the mosfet, enabling input slew rates that ri val op amps using bipolar input stages. the added advantage fo r high impedance, precision amplifiers is the lack of a sign ificant 1/f component of current noise (figures 15, 16) as there is virtually no gate current. the input stage jfets are bootstra pped to maintain a constant jfet drain to source voltage whic h keeps the jfet gate currents and input stage frequency response nearly constant over the common mode input range of th e device. these enhancements provide excellent cmrr, ac performance and very low input distortion over a wide temperature range. the common mode input performance for offset voltage and bias current is shown in figure 44. note that the input bias current remains low even after the maximum input stage common mode voltage is exceeded (as indicated by the abrupt change in input offset voltage). output drive capability the complementary bipolar emitter follower output stage features low output impedance (figure 42) and is capable of substantial current drive over the full temperat ure range (figures 29, 30) while driving the output voltage close to the supply rails. the output current is internally limited to approximately 50ma at +25c. the amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. this applies to only 1 amplifier at a time for the dual op amp. continuous operation under these conditions may degrade long term reliability. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl28110 and isl28210 are immune to output phase reversal, out to 0.5v beyond the rail (v abs max) limit. beyond these limits, the device is still immune to reversal to 1v beyond the rails but damage to the internal esd protection diodes can result unless these input currents are limited. maximizing dynamic signal range the amplifiers maximum undistorted output swing is a figure of merit for precision, low distortion applications. audio amplifiers are a good example of amplifiers that require low noise and low signal distortion over a wide ou tput dynamic range. when these applications operate from batteries, raising the amplifier supply voltage to overcome poor output voltage swing has the penalty of increased power consumption and shorter battery life. amplifiers whose input and output stages can swing closest to the power supply rails while providing low noise and undistorted performance, will provide maximum useful dynamic signal range and longer battery life. rail-to-rail input and output (rrio) amplifiers have the highest dynamic signal range but their added complexity degrades input noise and amplifier distortion. many contain two input pairs, one pair operating to each supply rail. the trade-offs for these are increased input noise and distortion caused by non-linear input bias current and capacitance when amplifying high impedance sources. their rail-to-rail output stages swing to within a few millivolts of the rail, but output impedances are high so that their output swing decreases and dist ortion increases rapidly with increasing load current. at heavy load currents the maximum output voltage swing of rro op amps can be lower than a good emitter follower output stage. the isl28110 and isl28210 low noise input stage and high performance output stage are optimized for low thd+n into moderate loads over the full -40c to +125c temperature range. figures 21 and 22 show the 1khz thd+n unity gain performance vs output voltage sw ing at load resistances of 2k ? and 600 ? . figure 45 shows the unity-gain thd+n performance driving 600 ? from 5v supplies. figure 43. input esd diode current limiting - + r in - r l v in - v+ v- r in + v in + figure 44. input offset voltage and bias current vs common mode input voltage v cm (v) n o r m a l i z e d i n p u t b i a s c u r r e n t ( p a ) -10 -8 -6 -4 -2 0 2 4 6 8 10 -15 -10 -5 0 5 10 15 -500 -400 -300 -200 -100 0 100 200 300 400 500 n o r m a l i z e d v os ( u v ) v s = 15v t = +25 c input offset voltage (v os ) input bias (i b ) isl28110, isl28210 16 fn6639.2 september 14, 2011 power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions , or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance isl28110 and isl28210 spice model figure 46 shows the spice model schematic and figure 47 shows the net list for the spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. ac parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, cmrr, gain and phase. the dc parameters are i os , total supply current and output voltage swing. the model uses typical parameters given in the ?electrical specifications? table beginning on page 4. the avol is adjusted for 125db with the dominant pole at 7hz. the cmrr is set 120db, f = 280khz. the input stage models the actual device to present an accurate ac representation . the model is configured for ambient temperature of +25c. figures 48 through 61 show the characterization vs simulation results for the noise voltage, closed loop gain vs frequency, small signal 0.1v step, large signal 5v step response, open loop gain phase, cmrr and output voltage swing for 5v and 15v supplies. license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licence to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, re nt, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including buy not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and the macro-model without prior notice. figure 45. unity-gain thd+n vs output voltage vs temperature at v s = 5v for 600 load 0.0001 0.001 0.01 0.1 1 012345678910 v p-p (v) thd+n (%) v s = 5v r l = 600 a v = 1 +25c 0c -40 c +125c +85c t jmax t max ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ( - v outmax ) v outmax r l ------------------------ + = (eq. 2) isl28110, isl28210 17 fn6639.2 september 14, 2011 vout vc 5 vout vmid vmid vmid v-- vmid common mode gain stage with zero vout correction current output stage sources vcm vout input stage gain stage mid supply ref v vout vout 29 vout 38 3 14 23 33 34 15 13 vin- v-- 8 v++ v++ v++ v++ v-- 27 35 v+ vg 26 v- v-- 4 36 25 v-- 16 17 19 vin+ 11 32 31 12 18 5 7 9 10 28 21 vc 1 20 22 37 2 24 30 6 0 0 0 0 r3 5e11 r3 5e11 c2 4e-12 c2 4e-12 v2 0.7vdc v2 0.7vdc c6 10e-12 10e-12 v3 0.7vdc v3 0.7vdc l1 5.30532e-10 l1 5.30532e-10 + - g + - g15 g gain = 20e-3 v9 .523 v9 .523 + - g13 g gain = 1.11e-2 + - g13 v7 1.18 v7 dx d6 dx d6 r11 1k r11 1k dx d5 dx d5 v4 1.18 v4 1.18 v1 0.4 v1 0.4 r2 5e11 r2 5e11 r22 318.319274232055 318.319274232055 + - g6 g gain = 1 + - g6 g gain = 1 dx d7 dx d7 c9 10e-12 c9 10e-12 r1 110 r1 110 r14 200k r14 200k c4 2.5e-12 + - g1 g gain = 33 + - g1 q7 pnp_mirror q7 pnp_mirror j1 pj110_input j1 pj110_input + - g11 g gain = 0.0031415 + - g11 isy 2.5e-3 isy 2.5e-3 dn d1 dn d1 + - g9 g gain = 0.0031415 + - g9 gain = 0.0031415 j3 pj110_cascode j3 pj110_cascode dy d13 dy d13 dx d15 dx d15 q2 npn_cascode q2 npn_cascode r15 0.001 q4 npn_cascode q4 npn_cascode d3 dbreak d3 dbreak - + + - buffer1 e - + + - buffer1 e r10 1 1 dx d12 dx d12 c3 6e-12 c3 - + + - e2 e gain = 0.5 - + + - e2 gain = 0.5 + - g8 g gain = 1 + - g8 g gain = 1 v5 1.18 v5 1.18 r9 1 r9 1 dy d16 dy d16 dx d10 dx d10 dx d9 dx d9 r6 5.5k r6 5.5k dx d8 dx r4 250 r4 250 q1 npn_cascode q1 npn_cascode + - g7 g gain = 1 + - g7 gain = 1 l3 l3 5.30532e-10 c7 10e-12 c7 10e-12 cin2 7.27e-40 7.27e-40 r7 250 r7 250 r8 100 r8 100 v8 .523 v8 .523 - + + - buffer2 e - + + - buffer2 e q6 pnp_mirror q6 pnp_mirror - + + - e4 e gain = 1 - + + - e4 + - g4 g gain = 181.819e-6 + - g4 g gain = 181.819e-6 j2 pj110_input j2 pj110_input r16 0.001 r16 0.001 q5 npn_cascode q5 npn_cascode l2 5.30532e-10 d2 dbreak d2 dbreak r12 1e10 r12 1e10 cindif 5.87e-40 5.87e-40 r17 0.001 + - g12 g gain = 0.0031415 + - g12 g gain = 0.0031415 - + + - en e gain = 1 - + + - en e gain = 1 r19 318.319274232055 r19 318.319274232055 + - g2 g gain = 33 + - g gain = 33 + - g14 g gain = 1.11e-2 + - g14 5.30532e-10 l4 5.30532e-10 j4 pj110_cascode pj110_cascode d4 dbreak d4 dbreak v6 1.18 v6 1.18 r24 50 r24 50 r23 50 dx d11 dx d11 - + + - eos e gain = 1 - + + - eos e gain = 1 + - g3 g gain = 181.819e-6 + - g3 g gain = 181.819e-6 r20 318.319274232055 318.319274232055 r21 318.319274232055 r21 318.319274232055 i1 240e-6 i1 240e-6 c1 4e-12 c1 4e-12 r13 200k dx d14 dx d14 + - g5 g gain = 1 + - g5 gain = 1 ios 0.3e-12 ios + - g10 g gain = 0.0031415 + - g10 g gain = 0.0031415 r5 5.5k r5 5.5k cin1 7.27e-40 7.27e-40 c8 10e-12 10e-12 c5 2.5e-12 - + + - e3 e gain = 1 - + + - e3 e gain = 1 + - g16 g gain = 20e-3 + - g r18 0.001 r18 0.001 v++ vg vmid vmid vc v-- vcm v++ vg vmid vc v-- vcm figure 46. spice net list isl28110, isl28210 18 fn6639.2 september 14, 2011 * source isl28110_210_presubckt_0 * revision a, lafontaine nov 4th 2010 * model for noise 200nv/rthz@0.1hx *11nv/rthz base band, supply current 2.5ma, *cmrr 120db fcm=281khz ,avol 125db *fd=7hz * sr = 20v/us, gbwp 12.6mhz, output *voltage clamp *copyright 2010 by intersil corporation *refer to data sheet ?license statement? *use of this model indicates your acceptance *with the terms and provisions in the license *statement. * connections: *+input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28110subckt vin+ vin- v+ v- vout * source isl28110_210_presubckt_0 * *voltage noise * e_en vin+ 4 2 0 1 v_v1 1 0 0.4 d_d1 1 2 dn r_r1 2 0 110 * *input stage * r_r2 vin- 3 5e11 r_r3 3 4 5e11 c_cindif 4 vin- 5.87e-40 c_cin1 v-- vin- 7.27e-40 c_cin2 v-- 4 7.27e-40 i_ios 4 vin- dc 0.3e-12 r_r4 5 vin- 250 j_j1 7 5 6 pj110_input j_j2 15 16 14 pj110_input j_j3 v-- 14 15 pj110_cascode j_j4 v-- 6 7 pj110_cascode q_q1 19 13 14 npn_cascode q_q2 12 13 6 npn_cascode q_q4 8 13 6 npn_cascode q_q5 12 13 14 npn_cascode q_q6 19 11 20 pnp_mirror q_q7 8 11 9 pnp_mirror v_v2 v++ 10 0.7vdc v_v3 v++ 21 0.7vdc r_r5 9 10 5.5k r_r6 20 21 5.5k e_buffer1 11 v++ 8 v++ 1 e_buffer2 13 v-- 12 v-- 1 d_d2 8 19 dbreak d_d3 19 8 dbreak i_i1 v++ 12 dc 240e-6 c_c1 19 v++ 4e-12 c_c2 v-- 19 4e-12 r_r7 16 17 250 e_eos 17 4 vc vmid 1 * *1st gain stage * r_r8 18 v++ 100 d_d4 v-- 18 dbreak d_d5 22 v++ dx d_d6 v-- 24 dx v_v4 22 23 1.18 v_v5 23 24 1.18 g_g1 v++ 23 19 8 33 g_g2 v-- 23 19 8 33 r_r9 23 v++ 1 r_r10 v-- 23 1 r_r11 25 23 1k d_d7 25 vmid dx d_d8 vmid 25 dx r_r12 25 vmid 1e10 g_g3 v++ vg 25 vmid 181.819e-6 g_g4 v-- vg 25 vmid 181.819e-6 d_d9 26 v++ dx d_d10 v-- 27 dx v_v6 26 vg 1.18 v_v7 vg 27 1.18 r_r13 vg v++ 200k r_r14 v-- vg 200k c_c3 8 vg 6e-12 c_c4 vg v++ 2.5e-12 c_c5 v-- vg 2.5e-12 * * mid supply reference * e_e2 vmid v-- v++ v-- 0.5 e_e3 v++ 0 v+ 0 1 e_e4 v-- 0 v- 0 1 i_isy v+ v- dc 2.5e-3 * *common mode gain stage 40db/dec * g_g5 v++ 29 3 vmid 1 g_g6 v-- 29 3 vmid 1 g_g7 v++ vc 29 vmid 1 g_g8 v-- vc 29 vmid 1 l_l1 28 v++ 5.30532e-11 l_l2 30 v-- 5.30532e-11 l_l3 31 v++ 5.30532e-11 l_l4 32 v-- 5.30532e-11 r_r15 29 28 0.001 r_r16 30 29 0.001 r_r17 vc 31 0.001 r_r18 32 vc 0.001 * *second pole stage 40db/dec * g_g9 v++ 33 vg vmid 0.0031415 g_g10 v-- 33 vg vmid 0.0031415 g_g11 v++ 34 33 vmid 0.0031415 g_g12 v-- 34 33 vmid 0.0031415 r_r19 33 v++ 318.319274232055 r_r20 v-- 33 318.319274232055 r_r21 34 v++ 318.319274232055 r_r22 v-- 34 318.319274232055 c_c6 33 v++ 10e-12 c_c7 v-- 33 10e-12 c_c8 34 v++ 10e-12 c_c9 v-- 34 10e-12 * * output stage * d_d11 34 35 dx d_d12 36 34 dx d_d13 v-- 37 dy d_d14 v++ 37 dx d_d15 v++ 38 dx d_d16 v-- 38 dy g_g13 37 v-- vout 34 1.11e-2 g_g14 38 v-- 34 vout 1.11e-2 g_g15 vout v++ v++ 34 20e-3 g_g16 v-- vout 34 v-- 20e-3 v_v8 35 vout -.384 v_v9 vout 36 -.384 r_r23 vout v++ 50 r_r24 v-- vout 50 * * .model pj110_input pjf + vto=-1.4 + beta=0.0025 + lambda=0.03 + is=2.68e-015 + pb=0.73 + cgd=8.6e-012 + cgs=9.05e-012 + fc=0.5 kf=0 + af=1 + tnom=35 * .model npn_cascode npn + is=5.02e-016 + bf=150 + va=300 + ik=0.017 + rb=0.01 + re=0.011 + rc=900 + cje=2e-013 + cjc=1.6e-028 + kf=0 + af=1 * .model pj110_cascode pjf + vto=-1.4 + beta=0.000617 + lambda=0.03 + is=3.96e-016 + pb=0.73 + cgd=2.2e-012 + cgs=3e-012 + fc=0.5 + kf=0 + af=1 + tnom=35 * .model dbreak d + bv=43 + rs=1 * .model pnp_mirror pnp + is=4e-015 + bf=150 + va=50 + ik=0.138 + rb=0.01 + re=0.101 + rc=180 + cje=1.34e-012 + cjc=4.4e-013 + kf=0 + af=1 * .model dn d(kf=6.69e-12 af=1) .model dx d(is=1e-12 rs=0.1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28110subckt figure 47. spice net list isl28110, isl28210 19 fn6639.2 september 14, 2011 characterization vs simulation results figure 48. characterized input noise voltag e figure 49. simulated input noise voltage figure 50. characterized closed loop gain vs frequenc y figure 51. simulated closed loop gain vs frequency figure 52. characterized small signal transient response vs r l , v s = 0.9v, 2.5v figure 53. simulated small sign al transient response vs r l , v s = 0.9v, 2.5v 1 10 100 1000 1 10 100 1000 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) v s = 18v input noise voltage 10 100 1000 frequency (hz) 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) v s = 18v input noise voltage -10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m 100m g a i n ( d b ) frequency (hz) a cl = 1 a cl = 10 a cl = 100 a cl = 1000 v s = 5v & 15v c l = 4pf v out = 100mv p-p r l = open r f = 100k ? , r g = 100 ? r f = 100k ? , r g = 1k ? r f = 100k ? , r g = 10k ? r f = 0, r g = 1k 10k 100k 1m 10m 100m frequency (hz) -10 0 10 20 30 40 50 60 70 g a i n ( d b ) a cl = 1 a cl = 10 a cl = 100 a cl = 1000 r f = 100k ? , r g = 100 ? r f = 100k ? , r g = 1k ? r f = 100k ? , r g = 10k ? r f = 0, r g = v s = 5v & 15v c l = 4pf v out = 100mv p-p r l = open -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v o u t ( v ) time (s) v s = 15v a v = 1 r l = 2k c l = 4pf -0.15 -0.10 -0.05 0 0.05 0.10 0.15 v o u t ( v ) 0 0.2 0.4 0.6 0.8 1.0 time (s) v s = 15v a v = 1 r l = 2k c l = 4pf isl28110, isl28210 20 fn6639.2 september 14, 2011 figure 54. characterized large signal transient response vs r l , v s = 0.9v, 2.5v figure 55. simulated large sign al transient response vs r l , v s = 0.9v, 2.5v figure 56. simulated (design) open-loop gain, phase vs frequency figure 57. simulated (spice) open-loop gain, phase vs frequency figure 58. simulated (design) cmrr figure 59. simulated (spice) cmrr characterization vs simulation results (continued) -6 -4 -2 0 2 4 6 012345678910 v o u t ( v ) time (s) v s = 15v a v = 1 r l = 2k c l = 4pf -6 -4 -2 0 2 4 6 0246810 v o u t ( v ) time (s) v s = 15v a v = 1 r l = 2k c l = 4pf -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 100 1k 10k 100k 1m 10m 100m 1g g a i n ( d b ) frequency (hz) v s = 15v r l =1m ? gain phase -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 100 1k 10k 100k 1m 10m 100m 1g g a i n ( d b ) frequency (hz) v s = 15v r l =1m ? gain phase 0.1 1 10 100 1k 10k 100k 1m 10m 100m c m r r ( d b ) frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 v s = 15v simulation 0.1 1 10 100 1k 10k 100k 1m 10m 100m c m r r ( d b ) frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 v s = 15v simulation isl28110, isl28210 21 fn6639.2 september 14, 2011 figure 60. simulated output voltage swing 5v figure 61. simulated output voltage swing 15v characterization vs simulation results (continued) 0 0.20.40.60.81.0 -5.0 0 5.0 time (m s) o u t p u t v o l t a g e s w i n g ( v ) v s = 5v -15v -10v -5v 0v 5v 10v 15v 0 0.2 0.4 0.6 0.8 1.0 time (m s) isl28110, isl28210 22 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6639.2 september 14, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl28110 , isl28210 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 7/14/11 fn6639.2 converted to new datasheet template. page 1 added "related literature" and "an1594: is l28210soiceval1z evaluati on board user?s guide" page 3 ordering information table: added isl28210soiceval1z evaluation board 11/29/10 fn6639.1 removed label on right side of char acterization curve, figure 48 (input noise current). 11/23/10 page 1 updated trademark statement page 3 ordering information: remo ved "coming soon" from isl28110fbz page 4 electrical specifications: added isl28110 ib and ios specs @ vs=5v. page 5 electrical specifications: ch anged avol limits fro v/mv to db page 5 electrical specifications, dynamic performance, slew rate: added "4v step" to conditions; changed typ limit from 23v/s to 20v/s page 6 electrical specifications, dynamic performance, slew rate: added "10v step" to conditions; chan ged typ limit from 23v/s to 20v/s page 6 electrical specifications: added isl28110 ib and ios specs @ vs= 15v. changed avol limits from v/mv to db. changed ts, settlin g time to 0.1% from 0.9s to 1.3s and changed ts, settling time to 0.01% from 1.2s to 1.6s. page 7 replaced elect spec table notes 8 & 9 (note 8 "parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperatur e limits established by characterization and are not production tested./note 9 limits es tablished by characterization and are not production tested.)" with: "compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design." page 8 characteristic curves: added isl28110 i b vs temperature (fig 4) page 8 characteristic curves: added isl28110 i os vs temperature (fig 6) pages 17-21: added pspice model section 9/13/10 fn6639.0 initial release. isl28110, isl28210 23 fn6639.2 september 14, 2011 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7. isl28110, isl28210 24 fn6639.2 september 14, 2011 package outline drawing m8.118 8 lead mini small outline plastic package rev 3, 3/10 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.036 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m isl28110, isl28210 25 fn6639.2 september 14, 2011 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b? |
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